Field of the Invention
The present invention relates to a voltage regulator capable of improving overshoot characteristics of the voltage regulator.
Description of the Related Art
As illustrated in FIG. 4, a related-art voltage regulator includes: a voltage regulator control circuit including an amplifier 402 supplied with power from a current source 403, the amplifier 402 being configured to amplify a voltage difference between a reference voltage VREF of a voltage source 401, and a voltage of a node between resistors 405 and 406 forming a voltage divider circuit for dividing a voltage of an output terminal 407 of the voltage regulator (hereinafter referred to as “VOUT”); an output transistor 404 configured to be controlled based on an output voltage of the amplifier 402; and overshoot suppression means 400 including a resistor 411, a capacitor 412, and a transistor 413. The related-art voltage regulator is operated with a positive power supply voltage (hereinafter referred to as “VDD”).
When the output voltage of the amplifier 402 is represented by VERR, and the voltage of the node between the resistors 405 and 406 is represented by VFB, VERR is low if VREF>VFB is established, whereas VERR is high if VREF<VFB is established.
When VERR is low, an ON-resistance of the output transistor 404 is low and VOUT is high. In contrast, when VERR is high, the ON-resistance of the output transistor 404 is high and VOUT is low. In both the cases, VREF=VFB is established, and VOUT is kept constant.
Immediately after the voltage regulator is powered on, VOUT is still low and VREF>VFB is established. At this time, the output transistor 404 is controlled to have a low ON-resistance, and hence overshoot is liable to occur in VOUT. In order to cope with this, the transistor 413 is controlled to be on for a certain period that is determined based on a time constant of the resistor 411 and the capacitor 412 so that VERR becomes a voltage close to VDD. As a result, the output transistor 404 is controlled to be off, and consequently overshoot of VOUT may be suppressed (see, for example, Japanese Patent Application Laid-open No. 2004-252891).
However, in the related-art voltage regulator illustrated in FIG. 4, the transistor 413 is controlled to be off when overshoot of VOUT is being suppressed. Thus, if a load is connected to the output terminal 407 of the voltage regulator, undershoot may occur in VOUT.
That is, optimal overshoot suppression means differs depending on states of the power supply voltage and a load, but the related-art voltage regulator cannot deal with such changes in states, which is a problem.